发明名称 Magnetic memory and manufacturing method thereof
摘要 According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.
申请公布号 US9190453(B2) 申请公布日期 2015.11.17
申请号 US201514622027 申请日期 2015.02.13
申请人 发明人 Nakazawa Takashi;Asao Yoshiaki;Kajiyama Takeshi;Noma Kenji
分类号 H01L43/00;H01L27/00;H01L27/22;H01L43/12;H01L27/24;H01L43/08;H01L43/02;G11C11/16 主分类号 H01L43/00
代理机构 Holtz, Holtz, Goodman & Chick PC 代理人 Holtz, Holtz, Goodman & Chick PC
主权项 1. A magnetic memory comprising: a semiconductor substrate; a plurality of active areas formed on a surface of the semiconductor substrate; a plurality of word lines buried in the surface of the semiconductor substrate including the plurality of active areas, the plurality of word lines being parallel to a first direction; a plurality of select transistors provided on the plurality of active areas, wherein at least two of the plurality of select transistors are provided for each of the plurality of active areas, and a plurality of gate electrodes of the plurality of select transistors are used for the plurality of word lines; a plurality of variable resistance elements provided on the plurality of active areas, wherein at least two of the plurality of variable resistance elements are provided for each of the plurality of active areas, and the plurality of variable resistance elements are respectively connected to a plurality of drain regions of the plurality of select transistors; and a plurality of lower plugs provided on the plurality of active areas, wherein at least two of the plurality of the lower plugs are provided for each of the plurality of active areas, and the plurality of lower plugs are respectively provided between the plurality of drain regions of the plurality of select transistors and the plurality of variable resistance elements; wherein the plurality of lower plugs comprise a first lower plug, and the plurality of variable resistance elements comprise a first variable resistance element provided on the first lower plug, and a center of a top surface of the first lower plug is shifted from a center of a bottom surface of the first variable resistance element in a second direction, and the top surface of the first lower plug partially overlaps with the bottom surface of the first variable resistance element.
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