Digitally-programmable gain amplifier with direct-charge transfer and offset cancellation

摘要

A Programmable-Gain Amplifier (PGA) has a digital value that programmably adjusts the gain of the analog amplifier. A variable capacitor has several switched sub-capacitors that are enabled by the digital value. Enabled sub-capacitors are switched between a sampled input and a virtual ground on one terminal, and connect to a summing node on the other terminal. The summing node connects to the inverting input of an op amp either through a switch or through a double-sampling capacitor that stores an offset. A feedback capacitor is in parallel with a sampling capacitor during a second clock phase when direct-charge transfer occurs, reducing power consumption of the amplifier. The feedback capacitor samples the sampled input during the first clock phase. The PGA gain is proportional to the sum of capacitances of enabled sub-capacitors. The gain can be adjusted for sensor inputs to an Analog Front-End (AFE), such as for an electro-cardiogram (ECG).

主权项

1. A direct-charge-transfer switched-capacitor circuit having an amplifier gain that is digitally programmable comprising:
a digital input having a multi-bit digital value that is programmable to vary a gain of the direct-charge-transfer switched-capacitor circuit; an analog input; an op amp having a first input and a second input and an output; a sampling capacitor for storing sampled input charge that is sampled from the analog input during a first clock phase; a feedback capacitor that is connected to the output of the op amp and in parallel with the sampling capacitor during a second clock phase for direct charge transfer; a parallel capacitor network having a plurality of sub-capacitors that are enabled and disabled by the multi-bit digital value of the digital input; wherein a capacitance value of the parallel capacitor network is a sum of capacitance values of sub-capacitors that are enabled by the multi-bit digital value, wherein the parallel capacitor network has a variable capacitance that depends on the multi-bit digital value; wherein the plurality of sub-capacitors that are enabled sample the analog input during the first clock phase and drive stored sampled input charge to the first input of the op amp during the second clock phase; and a double-sampling capacitor connected between the plurality of sub-capacitors and the first input of the op amp, wherein the stored sampled input charge is driven to double-sampling capacitor and charge is coupled through the double-sampling capacitor to the first input of the op amp during the second clock phase.