| 发明名称 | Semiconductor device comprising capacitor and method of manufacturing the same | ||
| 摘要 | A semiconductor device includes an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface, a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface, a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug, a first metal electrode pattern on the first dielectric layer pattern, a first upper plug electrically connected to the first metal electrode pattern, and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug. | ||
| 申请公布号 | US9190402(B2) | 申请公布日期 | 2015.11.17 |
| 申请号 | US201414245079 | 申请日期 | 2014.04.04 |
| 申请人 | Samsung Electronics Co., Ltd. | 发明人 | Kim Yoon-Hae;Rhee Hwa-Sung |
| 分类号 | H01L21/02;H01L27/01;H01L23/522;H01L49/02;H01L21/768;H01L27/108 | 主分类号 | H01L21/02 |
| 代理机构 | Harness, Dickey & Pierce, P.L.C. | 代理人 | Harness, Dickey & Pierce, P.L.C. |
| 主权项 | 1. A semiconductor device, comprising: an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface; a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface; a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug; a first metal electrode pattern on the first dielectric layer pattern; a first upper plug electrically connected to the first metal electrode pattern; and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug. | ||
| 地址 | Gyeonggi-do KR | ||