Apparatus and method for operating a processor with an operation cache

摘要

A processor includes a computation engine to produce a computed value for a set of operands. A cache stores the set of operands and the computed value. The cache is configured to selectively identify a match and a miss for a new set of operands. In the event of a match the computed value is supplied by the cache and a computation engine operation is aborted. In the event of a miss a new computed value for the new set of operands is computed by the computation engine and is stored in the cache.

主权项

1. A method, comprising:
simultaneously applying operands and a received operation code to a computation engine circuit component and a cache; using the operands at the computation engine circuit component to speculatively compute a related value based upon a speculative operation code; loading the speculative operation code and the related value into the cache; comparing the operands to stored operands in the cache to selectively identify a match and a miss; outputting from the cache a stored value in the event of a match; outputting from the computation engine circuit component a computed value in the event of a miss; and storing the received operation code, the speculative operation code, the operands, the related value and the computed value in the same cache line.