用以制造半导体结构之方法及用于检查复数覆盖标记之系统;METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE AND SYSTEM FOR INSPECTING OVERLAY MARKS

摘要

本发明提供一种用以制造一半导体结构之方法，包括：提供一基板以及形成在该基板上之一图样层，一或多个覆盖标记形成在该图样层上；使用一明视野(bright field)检查工具执行一预成膜(pre-film-formation)覆盖检查，以接收在该图样层上之该一或多个覆盖标记上之一预成膜资料；形成一或多层在该图样层上；使用一暗视野(dark field)检查工具执行一后成膜(post-film-formation)覆盖检查，以接收在该一或多层下面的该一或多个覆盖标记之一后成膜资料；以及决定该预成膜资料是否匹配该后成膜资料。; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data.