| 摘要 |
PURPOSE:To decrease the number of decoder loads, to the operating current by half, and to reduce the power consumption of decoder circuits, by constituting a circuit of decorders arranged for 2<n> decoders altogether. CONSTITUTION:A circuit is constituted that one load MOS transistor (TR) is used in common with four NOR gates AB1-AB4. The source of one load TR is branched into two, which are respectively couple with each NOR gate of word lines W1, W2 and that of word lines W3, W4 via each TR to which complementary bit signals are applied for the gates. The source of the TR is branched into two, which are coupled to the NOR gate AB1 corresponding to the word line W1 and the NOR gate AB2 corresponding to the word line W2 via each TR having complementary gate signal. Similarly, the source of the TR of a gate signal A0 is branched into two, which are coupled to the NOR gate AB3 corresponding to the word line W3 and the NOR gate AB4 corresponding to the word line W4 via each TR having complementary gate signal. |
