PARALLEL SLICE PROCESSOR WITH DYNAMIC INSTRUCTION STREAM MAPPING

摘要

A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis, permitting the mixture of those instruction types. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

主权项

1. A processor core, comprising:
a plurality of dispatch queues for receiving instructions of a corresponding plurality of instruction streams; a plurality of parallel instruction execution slices for executing the plurality of instruction streams in parallel; and a dispatch routing network for routing the output of the dispatch queues to the instruction execution slices such that the routing network dynamically varies the relationship between the dispatch queues and the plurality of parallel instruction slices according to execution requirements for the plurality of instruction streams and resource availability in the plurality of parallel execution slices.