发明名称 ARITHMETIC PROCESSING DEVICE AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING DEVICE
摘要 PROBLEM TO BE SOLVED: To suppress an increase in the circuit scale of a circuit for controlling a data bypass.SOLUTION: An execution control unit 2 holds the instruction decoded by a decoder unit 1 and outputs executable instructions successively. A memory control unit 4 outputs an access request to a memory 5 on the basis of the memory access instruction received from the execution control unit 2. A second register 8 temporarily holds the data allocated in correspondence to a first register 7 that holds the data used for arithmetic by an arithmetic execution unit 3 and read out from the memory 5, before it is transferred to the first register 7. When the memory control unit 4 outputs a plurality of access requests on the basis of the memory access instruction and successively transfers the data read out from the memory 5 separately a number of times to the second register 8, a bypass control unit 6 causes the execution control unit 2 to output an arithmetic instruction at the time the data last read out from the memory 5 and transferred to the second register 8 is bypassed from the second register 8 to the arithmetic execution unit 3.
申请公布号 JP2015201026(A) 申请公布日期 2015.11.12
申请号 JP20140079229 申请日期 2014.04.08
申请人 FUJITSU LTD 发明人 SAKASHITA SOTA;YOSHIDA TOSHIO;AKIZUKI YASUNOBU
分类号 G06F9/38;G06F12/08 主分类号 G06F9/38
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