CIRCUIT, SEMICONDUCTOR DEVICE, AND CLOCK TREE

摘要

A circuit with a reduced leakage current is provided. A first transistor, a third transistor, and a second transistor are electrically connected in this order in series, a drain of the second transistor and a source of the third transistor are electrically connected to each other and are electrically connected to an output node. The first transistor is a p-channel transistor. The second and third transistors are n-channel transistors each including a semiconductor region including an oxide semiconductor. The third transistor functions as a switch that controls electrical connection between a drain of the first transistor and an output node of the circuit. In the standby mode, the third transistor is in an off state.

主权项

1. A circuit comprising:
an output node; a first node; a second node; a first transistor; a second transistor; and a third transistor, wherein the circuit has a function of performing arithmetic operation with one or more first signals and outputting a second signal from the output node, wherein a first power supply potential is input to the first node, wherein a second power supply potential is input to the second node, wherein the first power supply potential is higher than the second power supply potential, wherein the first transistor is a p-channel transistor, wherein the second transistor and the third transistor are n-channel transistors, wherein the second transistor includes an oxide semiconductor layer, wherein the third transistor includes an oxide semiconductor layer, wherein the first transistor, the third transistor, and the second transistor are electrically connected in this order in series, wherein a source of the first transistor is electrically connected to the first node, wherein a drain of the second transistor is electrically connected to the output node, wherein a source of the second transistor is electrically connected to the second node, wherein potentials of gates of the first transistor and the second transistor are controlled by the one or more first signals, and wherein a third signal is input to a gate of the third transistor.