发明名称 |
SEMICONDUCTOR DEVICE |
摘要 |
In a semiconductor device provided with a MOSFET part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer and a drift layer, the gate pad part includes: the low resistance semiconductor layer; the drift layer formed on the low resistance semiconductor layer; a poly-silicon layer constituting a conductor layer and a gate pad electrode formed above the drift layer over the whole area of the gate pad part with a field insulation layer interposed therebetween; and a gate oscillation suppressing structure where a p-type diffusion region electrically connected with the a source electrode layer and a p-type impurity non-diffusion region are alternately formed on a surface of the drift layer. |
申请公布号 |
US2015325691(A1) |
申请公布日期 |
2015.11.12 |
申请号 |
US201414647443 |
申请日期 |
2014.03.31 |
申请人 |
SHINDENGEN ELECTRIC MANUFACTURING CO., LTD. |
发明人 |
Miyakoshi Nobuki |
分类号 |
H01L29/78;H01L29/739;H01L29/423;H01L29/40;H01L29/06;H01L29/10;H01L29/08 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor device provided with an active element part and a gate pad part defined on a semiconductor substrate which is formed by laminating a low resistance semiconductor layer of a first conductive type or a second conductive type and a drift layer of a first conductive type to each other, wherein
the active element part includes: the low resistance semiconductor layer; the drift layer formed on the low resistance semiconductor layer; a base region of a second conductive type formed on a surface of the drift layer; a high concentration impurity diffusion region of a first conductive type formed on a surface of the base region; a gate electrode layer formed on the base region sandwiched between the high concentration impurity diffusion region and the drift layer with a gate insulation layer interposed therebetween; and a first electrode layer formed in contact with a surface of the high concentration impurity diffusion region and a surface of the base region in a state where the first electrode layer is insulated from the gate electrode layer with an interlayer insulation layer interposed therebetween, and the gate pad part includes: the low resistance semiconductor layer; the drift layer formed on the low resistance semiconductor layer; a conductor layer formed above the drift layer over the whole area of the gate pad part with a field insulation layer having a thickness of 200 nm to 500 nm interposed therebetween; and a gate oscillation suppressing structure where an impurity diffusion region of a second conductive type electrically connected with the first electrode layer and an impurity non-diffusion region of a second conductive type are alternately formed on a surface of the drift layer. |
地址 |
Chiyoda-ku, Tokyo JP |