DUTY CYCLE DETECTOR AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME

摘要

A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.

主权项

1. A duty cycle detector configured to control detection active periods of rising and falling clocks, in response to first and second control signals with different active periods.