发明名称 |
SYNCHRONIZATION OF ACTIVITY OF MULTIPLE SUBSYSTEMS IN A SoC TO SAVE STATIC POWER |
摘要 |
The present disclosure relates to synchronization and parallel operation of two or more cores within a multi-core computing system so as to reduce an amount of time that all cores are operating during a processing period and thereby increase an amount of idle time per processing period. In this way deeper sleep and/or idle states for the cores and the system can be entered. |
申请公布号 |
US2015323975(A1) |
申请公布日期 |
2015.11.12 |
申请号 |
US201414275563 |
申请日期 |
2014.05.12 |
申请人 |
Qualcomm Innovation Center, Inc. |
发明人 |
Ambapuram Sravan Kumar;Vanka Krishna V.S.S.S.R.;Agarwal Shirish Kumar |
分类号 |
G06F1/32;G06F13/42;G06F13/28 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
1. A multi-core system comprising:
a peripheral memory device comprising data to be read and processed; a controller that sends a control signal once per processing period; a memory; a first core coupled to the memory and coupled to the controller and comprising a non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to perform a method for operating the core, the method comprising:
receiving a first instance of the control signal and then:
reading a first portion of the data from the peripheral memory device;processing the first portion of the data;converting the first portion of data to a processed first portion of the data; andwriting the processed first portion of the data to the memory;receiving a second instance of the control signal and then:
reading a second portion of the data from the peripheral memory device; and a second core coupled to the memory and coupled to the controller and comprising a non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to perform a method for operating the core, the method comprising:
receiving a second instance of the control signal; andreading the processed first portion of the data from the memory. |
地址 |
San Diego CA US |