| 摘要 |
PROBLEM TO BE SOLVED: To reduce analysis time of conduction noise.SOLUTION: By extracting a connection of a wire connected through a plurality of vias from wires of a board to be analyzed, vias of the connection are simplified. A via model conversion step S2 converts a plurality of vias into "an equal bottom area model" or "an equal side area model" to simplify the vias. "The equal bottom area model" is used to convert a plurality of vias into one via having a bottom area equal to the sum of the bottom areas of the plurality of vias to simplify the vias. "The equal side area model" is used to convert a plurality of vias into one via having a side area equal to the sum of the side areas of the plurality of vias to simplify the vias. A suspended component analysis step S3 calculates suspended components (inductance, capacitance, resistance) of a circuit board based on the simplified via model. A conduction noise analysis step S4 uses a circuit simulator to analyze conduction noise while taking into account the calculated suspended components and the like. |
