IDENTIFYING THE CAUSE OF TIMING FAILURE OF AN IC DESIGN USING SEQUENTIAL TIMING

摘要

A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of nodes representing IC components. The method identifies several paths in the graph that each starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements to satisfy a set of timing constraints. For each identified path, the method determines the ratio of signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node. When the IC design fails timing constraints, the path that has a maximum determined ratio as a cause for timing failure.

主权项

1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the method comprising:
identifying a plurality of paths in the graph, each path starting from a timed source node and ending to a timed target node, each path comprising a plurality of clocked elements and a plurality of computational elements; optimizing the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths in the plurality of paths to satisfy a set of timing constraints; for each identified path, determining a ratio of data signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node; determining that the IC design fails a set of timing constraints when one or more of the paths have a ratio greater than one; and identifying a path in the plurality of paths that has a maximum determined ratio as a cause for timing failure.