| 摘要 |
Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line. |
| 主权项 |
1. A method for forming a nonvolatile memory assembly, the method comprising:
providing a partially manufactured semiconductor device comprising a transistor,
the transistor comprising a drain, a gate, and a source; forming a nonvolatile memory element comprising a first layer, a second layer, and a third layer, wherein the third layer is formed between the first layer and the second layer,
the nonvolatile memory element formed over the drain of the transistor,the first layer operable as a first electrode,the second layer operable as a second electrode and electrically coupled to the drain,the third layer operable as a resistive switching layer switchable between a first resistive state and a second resistive state different from the first resistive state; and forming a bit line, a word line, and a source line,
the bit line formed over the nonvolatile memory element and electrically coupled to the first layer of the nonvolatile memory element,the word line formed over the gate of the transistor and electrically coupled to the gate,the source line formed over the source of the transistor and electrically coupled to the source. |
