| 发明名称 |
HYBRID MEMORY CUBE SYSTEM INTERCONNECT DIRECTORY-BASED CACHE COHERENCE METHODOLOGY |
| 摘要 |
A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die. |
| 申请公布号 |
US2015324290(A1) |
申请公布日期 |
2015.11.12 |
| 申请号 |
US201514706516 |
申请日期 |
2015.05.07 |
| 申请人 |
Leidel John;Murphy Richard C. |
发明人 |
Leidel John;Murphy Richard C. |
| 分类号 |
G06F12/08;G06F13/16;G06F13/40 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A computing system comprising:
a plurality of host processors; and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors, an HMC device including:
a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; anda logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die. |
| 地址 |
McKinney TX US |
