METHOD AND APPARATUS FOR TEST TIME REDUCTION

摘要

In described examples of a circuit (100) for testing an integrated circuit (IC), the circuit (100) includes an input converter (104) that receives N scan inputs (102) and generates M pseudo scan inputs (106), where M and N are integers. A scan compression architecture (110) is coupled to the input converter (104) and generates P pseudo scan outputs (116) in response to the M pseudo scan inputs (106). An output converter (118) is coupled to the scan compression architecture (110) and generates Q scan outputs (120) in response to the P pseudo scan outputs (116), where P and Q are integers. The input converter (104) receives the N scan inputs (102) at a first frequency and generates the M pseudo scan inputs (106) at a second frequency. The output converter (118) receives the P pseudo scan outputs (116) at the second frequency and generates the Q scan outputs (120) at the first frequency.