发明名称 TRENCH INSULATED GATE MOS SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a trench insulated gate MOS semiconductor device which has low on-resistance, a large current density and high breakdown resistance at the time of avalanche breakdown, and which inhibits voltage overshoot at the time of turn-off.SOLUTION: A trench insulated gate MOS semiconductor device comprises a one-conductivity-type emitter region 53, an other-conductivity-type base region 52, trenches 61, a gate electrode 72, an emitter electrode, an other-conductivity-type collector layer 56, a collector electrode 73 and a one-conductivity-type field stop layer 55 with a diffusion depth from a rear face being equal to or larger than 10 μm, which are formed on a one-conductivity-type semiconductor substrate. The other-conductivity-type base region is partitioned into a first region and a second region 152 by a plurality of trenches, and the emitter electrode directly contacts the first region and the emitter electrode contacts the second region via local openings in an insulation film. The second region has a resistance component equal to or less than 100 m&OHgr;/cm2 per unit area, which is adjusted by formation intervals of the local openings 63 (contact holes).
申请公布号 JP2015201660(A) 申请公布日期 2015.11.12
申请号 JP20150122316 申请日期 2015.06.17
申请人 FUJI ELECTRIC CO LTD 发明人 YOSHIKAWA ISAO
分类号 H01L29/739;H01L29/78 主分类号 H01L29/739
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