发明名称 METHODS OF FORMING PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME
摘要 An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.
申请公布号 US2015325625(A1) 申请公布日期 2015.11.12
申请号 US201514804310 申请日期 2015.07.20
申请人 SEO Bum-Seok;KIM Ki-Joon;LEE Kil-Ho 发明人 SEO Bum-Seok;KIM Ki-Joon;LEE Kil-Ho
分类号 H01L27/22;H01L43/08;H01L43/02 主分类号 H01L27/22
代理机构 代理人
主权项 1. A semiconductor device, comprising: a substrate having a gate electrode formed thereon, the gate electrode extending in a second direction; a magnetic tunnel junction pattern overlying the gate electrode; an insulating interlayer covering the magnetic tunnel junction pattern; an insulation layer overlying the insulating interlayer, the insulation layer including a plurality of first and second trenches arranged in a staggered pattern; and a plurality of first and second bit lines on the insulating interlayer, the plurality of first and second bit lines respectively disposed in the plurality of first and second trenches that extend in a first direction substantially perpendicular to the second direction, the plurality of first and second bit lines electrically connected to the magnetic tunnel junction pattern, wherein the plurality of first bit lines and the plurality of second bit lines are arranged in the staggered pattern.
地址 Yongin-si KR