METHOD AND APPARATUS FOR TEST TIME REDUCTION USING FRACTIONAL DATA PACKING

摘要

An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

主权项

1. A circuit comprising:
an input converter configured to receive N scan inputs and configured to generate M pseudo scan inputs, where M and N are integers; a scan compression architecture coupled to the input converter and configured to generate P pseudo scan outputs in response to the M pseudo scan inputs; and an output converter coupled to the scan compression architecture and configured to generate Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers, and the input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.