OPTIMIZING IC PERFORMANCE USING SEQUENTIAL TIMING

摘要

A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes several nodes that represent IC components. The method identifies a path in the graph that starts from a timed source node and ends at a timed target node. The path has several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to a set of clocked elements without changing the position of any clocked element relative to the position of the computational elements in the path. The clock signal of at least one clocked element is skewed by more than a period of the clock signal. The method implements the IC design by using the optimized IC design.

主权项

1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the method comprising:
identifying a path in the graph starting from a timed source node and ending at a timed target node, the path comprising a plurality of clocked elements and a plurality of computational elements; optimizing the timing performance of the IC design by skewing clock signals to a set of clocked elements in the plurality of clocked elements without changing a position of any clocked element relative to a position of the computational elements in the path, the clock signal of at least one clocked element skewed by more than a period of said clock signal; and implementing the IC design using the optimized IC design.