发明名称 |
METHOD OF FABRICATING A CHARGE-TRAPPING GATE STACK USING A CMOS PROCESS FLOW |
摘要 |
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described. |
申请公布号 |
WO2015119893(A3) |
申请公布日期 |
2015.11.12 |
申请号 |
WO2015US14118 |
申请日期 |
2015.02.02 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
RAMKUMAR, KRISHNASWAMY;SHIH, HUI MEI |
分类号 |
H01L29/423;H01L21/02;H01L21/28;H01L29/51 |
主分类号 |
H01L29/423 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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