| 摘要 |
<p>An electronic device 20 has a clock path 24 for propagating a clock signal and a clock propagating element 26 on the clock path. An analogue element 30 coupled to the clock path 24 varies, in dependence on an analogue level of a first signal 32, a switching delay for the clock propagating element 26 to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops. The analogue element may have a variable resistance, current regulating element or a capacitive element selectively coupled, in dependence of the analogue level of the first signal.</p> |
