Low power digital fractional divider with glitchless output

摘要

A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.

主权项

1. A system for dividing a clock signal, the system comprising:
a first multiplexor configured to receive a plurality of phases of a clock signal and output a shifted clock signal that includes a glitch based on the plurality of phases of the clock signal, wherein the first multiplexor is configured to output the shifted clock signal by outputting at least a first phase from the plurality of phases of the clock signal based on a selection signal selecting the first phase for output by the first multiplexor and the first multiplexor is configured to subsequently output a second phase from the plurality of phases of the clock signal based on the selection signal selecting the second phase for output by the first multiplexor; a second multiplexor configured to receive a masking signal and the shifted clock signal including the glitch, and is configured to output the shifted clock signal without the glitch using the masking signal, wherein the selection signal is a delayed version of the masking signal; and a divider circuit configured to receive the shifted clock signal without the glitch and output a fractionally divided clock signal based on the shifted clock signal without the glitch.