PWM (pulse width modulation) signal outputting circuit and method of controlling output of PMW signal

摘要

A PWM (Pulse Width Modulation) signal outputting circuit includes a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting when a reset signal is input to the counting unit; a dead time value storage unit for storing a dead time value; and a plurality of PWM signal outputting units for setting a start setting value and a termination setting value. The PWM signal outputting unit generates a termination signal and a start signal. Further, the PWM signal outputting unit is configured to output a PWM signal, which is raised according to the start signal generated by itself and is decreased according to the termination signal generated by itself. Further, the PWM signal outputting units is configured to generate the termination signal when the counter value matches to the termination setting value generated by itself.

主权项

1. A PWM (Pulse Width Modulation) signal outputting circuit, comprising:
a counting unit for counting a number of clocks to output a counter value, and for resetting the counter value to resume counting when a reset signal is input to the counting unit; a dead time value storage unit for storing a dead time value; and a plurality of PWM signal outputting units for setting a start setting value and a termination setting value, each of the PWM signal outputting units being configured to generate a termination signal and a start signal, each of said PWM signal outputting units being configured to output a PWM signal, which is raised according to the start signal generated by itself and is decreased according to the termination signal generated by itself, each of said PWM signal outputting units being configured to generate the termination signal when the counter value matches to the termination setting value generated by itself, wherein said PWM signal outputting units includes a front stage PWM signal outputting unit for generating the PWM signal that is raised first, and a later stage PWM signal outputting unit for generating the PWM signal that is raised next after the PWM signal that is raised first, said later stage PWM signal outputting unit is configured to generate the start signal when a sum of the termination setting value generated by the front stage PWM signal outputting unit and the dead time value matches to the counter value, and when a difference between the start setting value generated by itself and the termination setting value generated by the front stage PWM signal outputting unit is smaller than the dead time value, said later stage PWM signal outputting unit is configured to generate the start signal when the start setting value generated by itself matches to the counter value, and when the difference is greater than the dead time value, said front stage PWM signal outputting unit is configured to generate the start signal when the dead time value matches to the counter value, and when the start setting value generated by itself is smaller than the dead time value, and said front stage PWM signal outputting unit is configured to generate the start signal when the start setting value generated by itself matches to the counter value, and when the start setting value generated by itself is greater than the dead time value.