发明名称 Digital predistortion of a power amplifier for signals comprising widely spaced carriers
摘要 Digital predistortion (“DPD”) of an RF power amplifier for signals comprising two widely spaced carrier clusters is proposed. The basis waveforms within the DPD are selected to allow for the use of a lower sampling rate. As one example, multi-carrier signals spanning 60 MHz of bandwidth may be linearized using a sample rate of 100 MHz for the DPD module and the observation path, as opposed to a sample rate exceeding 300 MHz (5 times Nyquist) used conventionally. A transmit (Tx) filter is located after the power amplifier to attenuate distortion modes exceeding the sampling rate used.
申请公布号 US9184710(B2) 申请公布日期 2015.11.10
申请号 US201213368125 申请日期 2012.02.07
申请人 Intel Corporation 发明人 Braithwaite Richard Neil
分类号 H04L27/00;H04L25/03;H04L25/49;H03F3/24;H03F1/32;H03F3/189;H04L27/36;H04B1/00;H04B1/04 主分类号 H04L27/00
代理机构 Schwegman Lundberg & Woessner, P.A. 代理人 Schwegman Lundberg & Woessner, P.A.
主权项 1. A predistortion linearized amplifier system for amplifying a communication signal comprising: a digital predistorter comprising: a first component signal path and a second component signal path, each component signal path comprising: an input, each input adapted to receive a signal component of a communication signal the communication signal having at least a first signal component comprising a first carrier cluster and a second separate signal components comprising a second carrier cluster separate from the first carrier cluster;up-sampler circuitry that receives the signal component from the input;input delay circuitry that receives a first up-sampled signal from the up-sampler;an intermodulation distortion product generator that receives the first up-sampled signal from the up-sampler and a second up-sampled signal from corresponding up-sampler circuitry of another component signal path;an addition circuit coupled to an output of input delay circuitry and an output of the intermodulation distortion product generator; anda multiplier coupled to an output of the addition circuit; combiner circuitry coupled to an output of the multiplier of the first component signal path and the multiplier of the second component signal path that generates a combined predistorted output signal; a digital to analog converter coupled to the combiner circuitry receive the combined predistorted output signal and provide an analog signal; and, a power amplifier coupled to the digital to analog converter and configured to amplify the analog signal to provide an amplified analog signal.
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