Central processor with multiple programmable processor units

摘要

A central processor for installation in an imaging device with a CMOS image sensor. The central processor had an image sensor interface for receiving data from the CMOS image sensor and multiple processing units configured to operate in parallel for processing data from the image sensor interface. Each of the processing units has rewritable memory for microcode that operatively controls that processing unit. The multiple processing units and the image sensor interface are integrated onto a single chip.

主权项

1. A processor for an imaging device, the processor comprising:
an image sensor interface for receiving data from an image sensor; multiple processing units configured to operate in parallel for processing data from the image sensor interface, wherein each of the multiple processing units includes rewritable memory for storing microcode to operatively control the processing unit; and an instruction input interface for receiving encoded data indicative of an image processing instruction executed by the multiple processing units, the instruction input interface being configured to decode the encoded data corresponding to the image processing instruction, wherein the multiple processing units, the instruction input interface, and the image sensor interface are integrated onto a single chip.