Low disturbance, power-consumption, and latency in NAND read and program-verify operations

摘要

A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge voltage and discharge time to achieve faster Read and Program-Verify speed, lower power consumption, lower latency, and lower word line disturbance for a reliable DRAM-like latch sensing. A reduced precharge voltage can be increased by M-fold (M≧2) using a Multiplier between each bitline and each Latch sense amplifier (SA). Between each Multiplier and each Latch SA, there is a Connector with two optional designs for either fully passing a sense voltage to the Latch SA with a same-polarity and value or reversing the polarity the sensing voltage with additional amplification. The Latch SA is configured to transfer stored threshold states of a memory cell into a bit of a page buffer.

主权项

1. A device with a high-density NAND (HiNAND) hierarchical-BL memory architecture for lowering disturbance, power-consumption, and latency in Read operation and Program-Verify operation, the device comprising:
a HiNAND array comprising a matrix of NAND memory cells divided by J number of Groups arranged along with a plurality of global bitlines (GBLs), J being an integer number, each Group comprising a plurality of top Group-BL-select transistors controlled by a first common gate signal for respectively connecting the plurality of GBLs to a plurality of local bitlines (LBLs) and a plurality of Group-BL-select transistors controlled by a second common gate signal for respectively connecting the plurality of LBLs to a common source line, along the plurality of LBLs each Group being divided into K number of blocks, K being an even integer number, each block comprising a plurality of strings of N memory cells connected in series having N rows, N being an integer number, each string being associated with one LBL via a string-BL-select transistor and associated with a local common source line via a string-SL-select transistor, each row of memory cells across all strings in a block being commonly gated by a word line (WL) signal, all strings in each neighboring pair of the K number of blocks sharing the same local common source line connected to the common source line via a block-SL-select transistor controlled by one of K/2 third common gate signals associated with each Group; a first plurality of data handling/control circuits respectively coupled to odd-numbered half of the plurality of GBLs of the HiNAND array, each of the first plurality of data handling/control circuits comprising a multiplier circuit, a connector circuit, a sense amplifier circuit, and a page buffer circuit to connect to one odd-numbered GBL from the HiNAND array; and a second plurality of data handling/control circuits respectively coupled to even-numbered half of the plurality of GBLs of the HiNAND array, the second plurality of data handling/control circuits being substantially redundant to the first plurality of data handling/control circuits; wherein J is at least 2 to make a ratio of a length of a LBL in one Group at least smaller than a length of a GBL through all J number of Groups for keeping a LBL capacitance smaller than a conventional GBL capacitance to provide a reduced precharge voltage outputted to the GBL by charge-sharing the GBL with the LBL in the Group for achieving multi-fold reduction in discharging time for faster Read and Program-Verify operations; wherein the multiplier circuit in each of the first and the second plurality of data handling/controlling circuits is configured to multiply the reduced precharge voltage by multi-fold before being coupled by the connector circuit to the corresponding sense amplifier circuit for properly sensing and transferring a digital signal associated with threshold states in a selected memory cell in the HiNAND array to one or more digital bits in the page buffer circuit with substantial reduction in power consumption, word-line Read and Verify disturbance, and operation latency.