Wafer-level chip scale package

摘要

A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.

主权项

1. A wafer-level chip scale package, comprising:
a semiconductor chip comprising a transistor formed therein; a first dielectric layer disposed on the semiconductor chip; a first redistribution trace disposed on the first dielectric layer and electrically connected with a first electrode of the transistor; a second dielectric layer disposed on the first redistribution trace; a first via disposed in the second dielectric layer and coupled with the first redistribution trace; and a first pad disposed on the second dielectric layer and electrically connected with the first redistribution trace through the first via; wherein the first redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction, wherein the first redistribution trace has a beginning portion at the first via and an end portion adjacent to a second via, the first via and the end portion of the first redistribution trace are spaced apart by a distance Lv, the first redistribution trace has a curvature length Ltrace from the first via to the end portion of the first redistribution trace, and the curvature length Ltrace is greater than the distance Lv.