Memory cell

摘要

Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh.

主权项

1. A cell structure comprising:
a first p-doped well in a substrate; a second p-doped well in the substrate; a first n-doped well in the substrate and disposed between the first p-doped well and the second p-doped well; a first group of transistors, respective first ones of the first group of transistors forming a first latch, respective second ones of the first group of transistors forming a second latch, the first group of transistors having respective active areas in the first p-doped well in the substrate, the first n-doped well in the substrate, or the second p-doped well in the substrate; a second group of transistors forming a cascaded device electrically coupled to the first latch and the second latch, the second group of transistors having an active area in the second p-doped well in the substrate; and a well strap structure comprising an active area electrically coupled to a power node or a ground node.