Microprocessor and method for using an instruction loop cache thereof

摘要

A microprocessor is provided, which includes a processor core and an instruction loop cache. The processor core provides a fetch address of an instruction stream. The fetch address includes a tag and an index. The instruction loop cache receives the fetch address from the processor core. The instruction loop cache includes a cache array and a tag storage. The cache array stores multiple cache entries. Each cache entry includes a tag identification (ID). The cache array outputs the tag ID of the cache entry indicated by the index of the fetch address. The tag storage stores multiple tag values and output the tag value indicated by the tag ID output by the cache array. The instruction loop cache determines whether a cache hit or a cache miss occurs based on a bitwise comparison between the tag of the fetch address and the tag value output by the tag storage.

主权项

1. A microprocessor, comprising:
a processor core, providing a fetch address of an instruction stream, wherein the instruction stream comprises one or more instructions, and wherein the fetch address comprises a tag and an index; and an instruction loop cache, receiving the fetch address from the processor core, comprising: a cache array, coupled to the processor core, storing a first predetermined number of cache entries, wherein each said cache entry comprises a tag identification (ID), and wherein the cache array outputs the tag ID of the cache entry indicated by the index of the fetch address; and a tag storage, coupled to the processor core and the cache array, configured to store a second predetermined number of tag values and output the tag value indicated by the tag ID output by the cache array, wherein the instruction loop cache determines whether a cache hit or a cache miss occurs based on a bitwise comparison between the tag of the fetch address and the tag value output by the tag storage.