High-speed low-latency current-steering DAC

摘要

A digital to analog converter (DAC) includes a quantity of N cells including a Least Significant Bit (LSB) cell, a Most Significant Bit (MSB) cell and, N−2 cells ordered therebetween. Each of the N cells is configured to carry a current of I, 2*I, 4*I, 8*I, . . . , 2^(N−1)*I, respectively. At least the LSB cell includes a first cell element and a second cell element driven by a first current input and a second current input, respectively. A difference between a magnitude of the first current input and a magnitude of the second input current is approximately equal to I.

主权项

1. A digital to analog converter (DAC), the DAC comprising:
a quantity of N binary cells including a Least Significant Bit (LSB) cell, a Most Significant Bit (MSB) cell and, N−2 cells ordered therebetween, wherein each of the N cells is configured to carry a current of I, 2*I, 4*I, 8*I, . . . , 2^(N−1)*I, respectively; wherein at least the LSB cell includes a first cell element and a second cell element driven by a first current input and a second current input, respectively, and wherein a difference between a magnitude of the first current input and a magnitude of the second current input is approximately equal to I.