发明名称 |
Memory sharing by processors |
摘要 |
A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via the second interfaces, the logic operatively coupled to the first and second interfaces. The method includes receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative. |
申请公布号 |
US9183150(B2) |
申请公布日期 |
2015.11.10 |
申请号 |
US201213707801 |
申请日期 |
2012.12.07 |
申请人 |
International Business Machines Corporation |
发明人 |
Caparros Cabezas Victoria;Jongerius Rik;Schmatz Martin L.;Stanley-Marbell Phillip |
分类号 |
G06F12/12;G06F12/08;G06F12/14;G06F13/16 |
主分类号 |
G06F12/12 |
代理机构 |
Cantor Colburn LLP |
代理人 |
Cantor Colburn LLP |
主权项 |
1. A method of memory sharing implemented by logic of a computer memory control unit, the control unit comprising at least one first interface and at least two second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N≧2 non-cooperative processors via a corresponding one of the at least two second interfaces, the logic operatively coupled to the first and second interfaces, the method comprising:
receiving, via the second interfaces, a request to access data of the main physical memory from a first processor of the set; evaluating if a second processor has previously accessed the data requested by the first processor; and deferring the request from the first processor when the evaluation is positive, or, granting the request from the first processor when the evaluation is negative; wherein at least two of the N≧2 non-cooperative processors are different from one another with respect to a virtual memory interface having different physical page sizes with respect to one another; and wherein the interfaces comprise both hardware connections and software to interpret control signals. |
地址 |
Armonk NY US |