Vertical gated access transistor

摘要

A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed in the while the second region of the substrate is masked.

主权项

1. A memory device comprising:
a silicon substrate having an array portion and a logic portion; a plurality of U-shaped semiconductor structures that are formed in the array portion of the substrate, wherein the U-shaped semiconductor structures are defined by a pattern of alternating deep and shallow trenches that are crossed by a pattern of intermediate-depth trenches having depths between those of the shallow and deep trenches, wherein each of the deep trenches, the shallow trenches and the intermediate-depth trenches have bottom silicon surfaces that define the depths of the trenches; and a plurality of transistor devices formed over the logic portion of the substrate, wherein the transistor devices include a gate oxide layer, an uncapped gate layer, and a sidewall spacer structure.