发明名称 Maintaining hardware resource bandwidth quality-of-service via hardware counter
摘要 Each time a currently scheduled virtual machine (VM) accesses a hardware resource over a bus for the hardware resource via the currently scheduled VM running on a processor, a hardware component adjusts a bandwidth counter associated with usage of the bus for the hardware resource, without involvement of the currently scheduled VM or a hypervisor managing the currently scheduled VM. Responsive to the bandwidth counter reaching a threshold value, the hardware component issues an interrupt for handling by the hypervisor to maintain bandwidth quality-of-service (QoS) of bus bandwidth related to the hardware resource. Upon expiration of a regular time interval prior to the bandwidth counter reaching the threshold value, the hardware component resets the bandwidth counter to a predetermined value associated with the currently scheduled VM, without involvement of the currently scheduled VM or the hypervisor; the hardware component does not issue an interrupt. The hardware resource can be memory.
申请公布号 US9183022(B2) 申请公布日期 2015.11.10
申请号 US201313780204 申请日期 2013.02.28
申请人 International Business Machines Corporation 发明人 Arges Christopher J.;Schopp Joel H.;Strosaker Michael T.;Fontenot Nathan D.;George Jeffrey D.;VanderWiele Mark
分类号 G06F9/46;G06F9/455 主分类号 G06F9/46
代理机构 代理人 Josephs Damion
主权项 1. A method comprising: storing in one or more hardware registers a first value and a second value, wherein the first value is associated with a first virtual machine (VM) and the second value is associated with a second VM, wherein when the first VM and not the second VM runs on a shared processor during the first VM's scheduled regular time interval, a hardware memory controller is to reset a bandwidth counter to the first value associated with the first VM by copying the first value from the one or more hardware registers, and then decrement the bandwidth counter, without involvement of any VM or the hypervisor, each time the first VM accesses a hardware memory over the bus when running on the shared processor, wherein when the second VM and not the first VM runs on the shared processor during the second VM's scheduled regular time interval, the hardware memory controller is to reset the bandwidth counter to the second value associated with the second VM by copying the second value from the one or more hardware registers, and then decrement the bandwidth counter, without involvement of any VM or the hypervisor, each time the second VM accesses the hardware memory over the bus when running on the shared processor, wherein the bandwidth counter tracks usage of the bus for the hardware memory by each VM of the first VM and the second VM on a per-VM basis; and responsive to the bandwidth counter reaching a zero value when the first or second VM running in the shared processor at the first or second VM's respective scheduled regular time interval, issuing an interrupt by the hardware memory controller for handling by the hypervisor to maintain bandwidth quality-of-service (QoS) of bus bandwidth related to the hardware memory, wherein the hardware memory and the hardware memory controller are each hardware different than the processor, wherein the bandwidth counter and the one or more hardware registers are implemented directly in hardware as opposed to being software-implemented and are directly accessible by the hardware memory controller.
地址 Armonk NY US