Automatic asynchronous signal pipelining

摘要

An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

主权项

1. An integrated circuit, said integrated circuit comprising:
a plurality of destination storage elements; a source of an asynchronous signal, said asynchronous signal provided to said destination storage elements with a first interconnect; a distribution network providing the output from a distribution buffer to said destination storage elements with a second interconnect; a pipeline having a first storage element and a second storage element, the pipeline inserted between said distribution buffer and the source of said asynchronous signal, the first storage element coupled with the first interconnect for receiving the asynchronous signal from the source of the asynchronous signal and providing the asynchronous signal to the second storage element, the second storage element providing the asynchronous signal to the distribution buffer with the second interconnect; a first clock distribution network providing a clock signal from a first clock source to the first storage element and the plurality of destination storage elements with a third interconnect; a second clock distribution network providing the clock signal from the first clock source to the second storage element with a fourth interconnect, wherein a delay of the second clock distribution network providing the clock signal to the second storage element is less than a delay of the first clock distribution network providing the clock signal to the first storage element.