Descending set verify for phase change memory

摘要

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

主权项

1. A method comprising:
applying a first bias pulse to a phase change memory (PCM) cell to place said PCM cell in a low-resistance state in response to a write command and in response to a comparison of a first measurement of current in said cell during verify with a first verify reference current value; and applying a second bias pulse to said PCM cell to place said PCM cell in said low-resistance state in response to a comparison of a second measurement of said current in said cell during verify with a second verify reference current value, wherein said second verify reference current value is less than said first verify reference current value.