Circuit and method for controlling MRAM cell bias voltages

摘要

A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

主权项

1. A memory comprising:
a memory array comprising:
a plurality of bit lines;a plurality of source lines;a plurality of word lines; anda plurality memory cells, each of the memory cells comprising:
a select device; anda memory device coupled in series with the select device, each memory cell configured to be coupled to one of the word lines, and selectively coupled between one of the bit lines and one of the source lines; a replica circuit comprising:
a replica bit line;a replica source line;a replica memory cell coupled between the replica bit line and the replica source line, the replica memory cell comprising:
a replica memory device; anda replica select device coupled to the replica memory device and having a control electrode and at least one current carrying electrode; and at least one regulator circuit coupled to the replica circuit and the memory array, the at least one regulator circuit configured to:
receive a plurality of feedback voltages from the replica circuit, including:
a first feedback voltage corresponding to a voltage between the replica select device and the replica memory device;a second feedback voltage corresponding to a voltage on the replica bit line;a third feedback voltage corresponding to a voltage on the replica source line; andregulate voltages of read/write circuitry corresponding to a selected memory cell of the plurality of memory cells, wherein the at least one regulator circuit regulates the voltages using the replica circuit including the plurality of feedback voltages received from the replica circuit, wherein the at least one regulator circuit is configured to:regulate a source line voltage on a selected source line or a bit line voltage on a selected bit line, wherein the selected memory cell is coupled between the selected source line and the selected bit line;regulate a word line voltage on a selected word line in response to a voltage across the control electrode of the replica select device and the at least one current carrying electrode of the replica select device; andregulate a memory device voltage across the memory device in response to a reference memory device voltage and a replica voltage across the replica memory device.