Enhanced I/O performance in a multi-processor system via interrupt affinity schemes

摘要

Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.

主权项

1. A system for controlling interrupt processing, the system comprising:
an adapter operable to generate an interrupt, wherein the interrupt is communicated over a channel selected from a plurality of channels and the interrupt is processed by a processor selected from a plurality of processors, wherein the processor is selected according to a first mapping and the channel is selected according to a second mapping, wherein the first mapping comprises an association between the processor and the interrupt, wherein the interrupt is mapped to the processor that requested an operation triggering the interrupt, the first mapping having a first group of assignments between one or more processors of the plurality of processors and a plurality of respective interrupt identifiers, and wherein the second mapping comprises an association between the interrupt and the channel and the second mapping is adaptable based on a usage of one or more processors of the plurality of processors as assigned in the first mapping, the second mapping having a second group of assignments between the plurality of respective interrupt identifiers and one or more channels of the plurality of channels.