DDR receiver enable cycle training

摘要

A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

主权项

1. A method, comprising:
sampling a data strobe signal for a plurality of memory cycles; determining a receiver enable phase based upon the sampled data strobe signal; performing at least one memory write cycle and at least one memory read cycle to read data written by the at least one memory write cycle at a selected memory clock frequency; training at least one read data strobe cycle associated with the memory read cycle, wherein training is performed at a one-quarter memory clock cycle offset from an optimal receiver enable delay phase; and determining a correct receiver enable delay in response to a successful read data strobe training cycle.