Method and semiconductor device for a dedicated startup sequence in a resonant converter

摘要

A method and semiconductor device for a resonant power converter includes logic circuitry that performs a dedicated startup sequence when power is first provided to the resonant converter. The logic circuitry can discharge the resonant capacitor, then iteratively pulse only an upper switch during a portion of the startup sequence, and measures the dead time between the half bridge signal starting to fall and the next time it finishes rising. If the dead time is greater that a startup exit value, which is based on the most recent upper switch on-time, then the upper switch on-time is incremented and the process is repeated until the dead time is less than the startup exit value, whereupon the startup logic transitions to conventional symmetric switching.

主权项

1. A method of operating a semiconductor device that includes a resonant converter controller, comprising:
pulsing a lower switch drive signal initially for a preselected initial lower switch on-time; pulsing an upper switch drive signal for a preselected initial upper switch on-time responsive to pulsing the lower switch drive signal initially; iteratively measuring a dead time between a falling edge and a subsequent rising edge of a half bridge signal responsive to pulsing the upper switch drive signal, comparing a present dead time of a present iteration to a present startup exit value for the present iteration that is based on a present upper switch on-time for the present iteration, and, when the present dead time of the present iteration is above the startup exit value, incrementing the upper switch on-time by a preselected factor and pulsing the upper drive signal for the incremented upper switch on-time responsive to an end of the rising edge of the half bridge signal; when the present dead time of an iteration is below the present startup exit value, pulsing the upper switch drive signal again at the present upper switch on-time and setting a lower switch on-time to the present upper switch on-time; and commencing symmetric switching where the upper switch signal on-time and lower switching signal on-time are equal, responsive to the present dead time exceeding the startup exit value.