发明名称 Method and apparatus for accessing data stored in a storage system that includes both a final level of cache and a main memory
摘要 A data access system including a processor having (i) one or more levels of cache, and (ii) a storage system that includes a main memory and a cache module. The cache module includes a controller and a final level of cache to be accessed by the controller prior to accessing the main memory. In response to data required by the processor not being cached within the one or more levels of cache of the processor, the processor generates an address of a physical location within the storage system. The controller converts the address of the physical location within the storage system into an address of a virtual location within the final level of cache. The address of the virtual location is useable by the cache module to determine whether the data required by the processor is cached within the final level of cache.
申请公布号 US9182915(B2) 申请公布日期 2015.11.10
申请号 US201514710988 申请日期 2015.05.13
申请人 Marvell World Trade Ltd. 发明人 Sutardja Sehat
分类号 G06F12/00;G06F3/06;G06F12/08;G06F12/10 主分类号 G06F12/00
代理机构 代理人
主权项 1. A data access system comprising: a storage system, wherein the storage system includes a main memory, anda cache module comprising a first controller and a cache, wherein the cache of the cache module is configured as a final level of cache to be accessed by the first controller prior to the first controller accessing the main memory; and a processor including one or more levels of cache, wherein in response to data required by the processor not being cached within the one or more levels of cache of the processor, the processor is configured to generate an address of a physical location to be accessed within the storage system in order to retrieve the data required by the processor,the first controller is configured to convert the address of the physical location to be accessed within the storage system into an address of a virtual location within the final level of cache, andthe address of the virtual location within the final level of cache is useable by the cache module to determine whether the data required by the processor is cached within the final level of cache.
地址 St. Michael BB