发明名称 CIRCUIT INTEGRE PRESENTANT PLUSIEURS BLOCS IDENTIQUES IDENTIFIES
摘要 An integrated circuit comprising N adjacent identical blocks indexed by index j, a current block connected to preceding and following blocks, each comprising identification circuits comprises: N ordered inputs indexed i, connected to N outputs of the preceding block of same index; and N ordered outputs indexed i, connected to N inputs of the following block of same index; each input for i≠N of the current block connected by routing line indexed to output i+1 of the current block; last input N of the current block not connected to output of the current block; and first output 1 of the current block not connected to input of the current block; each block comprising: a connection pad; and N logic gates indexed i, each gate comprising first and second inputs and an output, N buses indexed i comprising a line through N blocks, and connected to output of a logic gate.
申请公布号 FR3013175(B1) 申请公布日期 2015.11.06
申请号 FR20130060930 申请日期 2013.11.08
申请人 TRIXELL 发明人 CHARRIER LAURENT
分类号 H04N5/376;G11C8/12 主分类号 H04N5/376
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