PREVENTING BURIED OXIDE GOUGING DURING PLANAR AND FINFET PROCESSING ON SOI

摘要

A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.

主权项

1. A method for preventing damage to the insulator layer of a semiconductor device during fabrication of fin field effect transistor (FinFET) devices, the method comprising:
obtaining a material stack comprising an active semiconductor layer, an insulator layer, and an etch stop layer existing between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer by applying fin-array formation processes to the material stack, with the etch stop layer resistant to those fin-array formation processes that the etch stop layer is exposed to, such that the etch stop layer and the insulator layer are not damaged during fin-array formation; patterning the fin-array by applying fin-array patterning processes after the fin-array has been formed from the active semiconductor layer, with the etch stop layer resistant to those fin-array patterning processes that the etch stop layer is exposed to, such that the etch stop layer and the insulator layer are not damaged during fin-array patterning; and fabricating a FinFET device by applying FinFET fabrication processes after the fin-array has been patterned by the fin-array patterning processes, with the etch stop layer resistant to those FinFET fabrication processes that the etch stop layer is exposed to, such that the etch stop layer and the insulator layer are not damaged during FinFET fabrication.