SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

摘要

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

主权项

1. Software based digital phase locked loop circuitry comprising:
a phase domain calculator having a frequency command word input, a reference frequency clock input, a processing clock input, an integer feedback input, a fractional feedback input, and a digital local oscillator update output; a digitally controlled oscillator having an input coupled with the digital local oscillator update output and an output frequency clock output; an integer feedback block having an input coupled with the output frequency clock output and an output coupled with the integer feedback input; a fractional feedback block having an input coupled with the output frequency clock output and an output coupled with the fractional feedback input; and a programmable fractional-N clock divider having an input coupled with the output frequency clock output and a processing clock output coupled with the processing clock input.