发明名称 |
BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE |
摘要 |
A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer, with the dielectric layer having a recess therein. A silicon (Si) layer is deposited in the recess. An interconnect is formed by providing a barrier layer and a conductive layer in the recess over the Si layer. The Si layer has a density that prevents or substantially prevents the barrier layer from moving away from the conductive layer and towards the dielectric layer during subsequent processing of the interconnect structure. |
申请公布号 |
US2015318207(A1) |
申请公布日期 |
2015.11.05 |
申请号 |
US201514797273 |
申请日期 |
2015.07.13 |
申请人 |
Taiwan Semiconductor Manufacturing Company Limited |
发明人 |
LIOU JOUNG-WEI;LIN KENG-CHU |
分类号 |
H01L21/768;H01L23/532;H01L23/528;H01L23/522 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
1. A method of fabricating an interconnect structure on a wafer, the method comprising:
providing a dielectric layer on the wafer, the dielectric layer having a recess therein; depositing a silicon (Si) layer in the recess; forming an interconnect by providing a barrier layer and a conductive layer in the recess over the Si layer; forming a nitride layer in a first portion of the Si layer that is adjacent to a top surface of the dielectric layer; and forming an oxide layer in a second portion of the Si layer that is adjacent to the first portion. |
地址 |
Hsinchu TW |