| 主权项 |
1. A symbol clock recovery circuit comprising:
an ADC comprising an ADC input terminal, an ADC output terminal and an ADC clock terminal, wherein the ADC input terminal is configured to receive a baseband signal, wherein the baseband signal is representative of one or more symbols, and wherein the ADC output terminal is configured to provide an ADC output signal; a controllable inverter comprising an inverter input terminal, an inverter output terminal and an inverter control terminal, wherein the inverter input terminal is configured to receive a carrier frequency signal, the inverter output terminal is configured to provide a configurable clock signal to the ADC clock terminal; and wherein the configurable clock signal is selectively inverted with respect to the received carrier frequency signal in accordance with a first feedback signal received at the inverter control signal; a timing detector comprising a timing detector input terminal, a timing detector output terminal, a first timing detector feedback terminal, wherein:
the timing detector input terminal is configured to receive the ADC output signal from the ADC output terminal;the timing detector output terminal is configured to provide a digital output signal; andthe first timing detector feedback terminal is configured to provide the first feedback signal to the inverter control terminal; wherein the timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal. |
