发明名称 Multi-Bit Standard Cells For Consolidating Transistors With Selective Sourcing
摘要 A method for designing a standard cell, e.g. a multi-bit flip-flop, can include identifying a first set of transistors. This first set functions to source power or ground to circuits of the standard cell. A second set of transistors can be determined and correlated. This second set forms at least part of the first set of transistors. Each correlated group in the second set of transistors receives identical signals, e.g. scan enable, reset, and/or set signals, and provides a same sourcing. A third set of transistors can then be created. This third set has fewer transistors than the second set. The second set of transistors can be deleted in the standard cell. The third set of transistors can be connected to the circuits of the standard cell. This method can significantly extend circuit consolidation to improve the area benefit of multi-bit standard cells.
申请公布号 US2015318845(A1) 申请公布日期 2015.11.05
申请号 US201414270311 申请日期 2014.05.05
申请人 Synopsys, Inc. 发明人 Pasternak John
分类号 H03K3/3562;G06F17/50 主分类号 H03K3/3562
代理机构 代理人
主权项 1. A method for designing a standard cell, the method comprising: identifying a first set of transistors, the first set of transistors functioning to source power or ground to circuits of the standard cell; determining and correlating a second set of transistors, the second set of transistors forming at least part of the first set of transistors, wherein each correlated group in the second set of transistors receives identical signals and provides a same sourcing; creating a third set of transistors, the third set of transistors being less than the second set of transistors; deleting the second set of transistors; and using a computer, connecting the third set of transistors to the circuits of the standard cell.
地址 Mountain View CA US