发明名称 |
FILLER BANK CONTROL CIRCUIT FOR SYNCHRONOUS FIFO QUEUES AND OTHER MEMORY DEVICES |
摘要 |
An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value. |
申请公布号 |
US2015317087(A1) |
申请公布日期 |
2015.11.05 |
申请号 |
US201414270165 |
申请日期 |
2014.05.05 |
申请人 |
Texas Instruments Incorporated |
发明人 |
Channabasappa Rakesh Yaraduyathinahalli;Patil Shekhar Dinkar;Suvarna Rajeev |
分类号 |
G06F3/06 |
主分类号 |
G06F3/06 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
a controller configured to generate multiple single-bit logic values, each single-bit logic value having one of: a first value indicating that a data packet has been written into a memory and a second value indicating that a data packet has been read from the memory; and logic circuitry configured to serially stack the single-bit logic values. |
地址 |
Dallas TX US |