DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS

摘要

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

主权项

1. A method of forming an integrated circuit (IC) package substrate, the method comprising:
laminating a first dielectric layer over a first metal feature; laser drilling a via in the dielectric layer to expose the first metal feature; laser patterning a trace in the dielectric laterally displaced from the via; electrolytically plating a fill metal into the via and the trace; planarizing the fill metal to a top surface of the dielectric layer; laminating and patterning dry resist film to expose via without exposing the trace; plating a surface finish metal over the exposed via fill metal; removing the dry film resist; and exposing the dielectric layer between the via and the trace.